Download e-book for iPad: Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current by P. van der Meer,A. van Staveren,Arthur H. M. van Roermund

By P. van der Meer,A. van Staveren,Arthur H. M. van Roermund

1. 1 Power-dissipation tendencies in CMOS circuits Shrinking equipment geometry, turning out to be chip region and elevated data-processing velocity functionality are technological traits within the built-in circuit to amplify chip performance. Already in 1965 Gordon Moore expected that the whole variety of units on a chip could double each year until eventually the Nineteen Seventies and each 24 months within the Eighties. This prediction is well known as "Moore's legislations" and finally culminated within the Semiconductor organization (SIA) know-how highway map [1]. The SIA highway map has been a consultant for the in­ dustry best them to endured wafer and die measurement development, elevated transistor density and working frequencies, and illness density aid. to say a number of numbers; the die measurement elevated 7% according to yr, the smallest characteristic sizes diminished 30% and the working frequencies doubled each years. because of those tendencies either the variety of transistors and the ability dissi­ pation consistent with unit zone elevate. within the close to destiny the utmost strength dissipation in keeping with unit region can be reached. Down-scaling of the provision voltage isn't just the best method to decrease strength dissipation quite often it is also an important precondition to make sure gadget reliability by means of lowering electric fields and gadget temperature, to avoid machine degradation. A draw-back of this answer is an elevated sign propa­ gation hold up, which ends up in a decrease data-processing pace performance.

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Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction (The Springer International Series in Engineering and Computer Science) by P. van der Meer,A. van Staveren,Arthur H. M. van Roermund


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